Project Goals Identify mitigation paths for solder joint yield loss caused during the SMT reflow soldering process specifically due to the excessive warpage of package and/or boards Evaluate these mitigation paths for their effectiveness in increasing solder joint yield despite high levels of package and/or board warpage © HDP User Group International, Inc. It will be non-package or non-PCB related © HDP User Group International, Inc. Objective Establish a limit for dynamic package warpage that can be mitigated during board assembly without impacting solder joint quality Need to set a baseline for today, and set what the limit is for all gaps. Project Scope - What is OUT of the Scope Package Warpage Mitigation Laminate Type Stack-up Die Thickness Die Size Package Warpage Measurement Metrologies Specifications Die FC BGA Package Substrate Package Substrate Printed Circuit Board Board Warpage Mitigation Laminate Type Stack-up Board Warpage Measurement Metrologies Specifications © HDP User Group International, Inc. Project Scope - What is IN the Scope FCBGA Package just as its entering the SMT Reflow Oven Die FC BGA Package Substrate Package Substrate Project Focus Area Printed Circuit Board Reflow Process Temperature –Time Profile Oven Atmosphere Solder Paste Rheology Wetting Metallurgy Activator chemistry Volume printed on land Surface Finish OSP/ENIG/ImAg/ENEPIG/ etc Package Termination Geometry (ball, pillar, column, etc) Metallurgy (SAC, low Ag SAC, BiSnAg, other) © HDP User Group International, Inc. Real Time Video of FCBGA Solder Joint Mechanism in Assembly Line Reflow Oven © HDP User Group International, Inc. All these are for FCBGA, Molded packages, QFN, Stretched joint Head on pillow bridging Various Solder Joint Defects can occur during SMT Reflow Soldering due to Excessive BGA component and/or Board Warpage © HDP User Group International, Inc. Package Substrate Die Board Head-on-Pillow Open Non –Wet Open Oxide layer or too solid to coelesce prior to soldification. © HDP User Group International, Inc.Ĥ Examples of Warpage Induced Defects for Area Array Solder Joints Thinner die the rigidness is loss and it can not control the substrate warpage. With advent of lead free soldering, the assembly temperatures have increased and the warpage impact has been exacerbated. Solder Joint Quality Impact of increasing Package and Warpage. Purpose Mitigate Area Array Solder Joint Quality Defects Generated by Package and / or Board Warpage during SMT Reflow Soldering © HDP User Group International, Inc.īackground Package/board Warpage increasing trends Driven by thinner package substrates and thinner die Package/Board contacts getting smaller and closer thereby reducing ability to overcome increased Warpage. FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar – INTEL HDP User Group Member Meeting Host: Dell/IBM Austin, Texas SeptemPresented by John Davignon © HDP User Group International, Inc.
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